The invention pertains to a data reduction circuit for reducing the number of bits of digital video signals with a differential pulse code modulator.
A data reduction circuit of this kind is described in an article in the periodical "Elektrisches Nachrichtenwesen", Vol. 58, 1984, pp. 447 to 449. The author of that article estimates that the prior art arrangement permits a clock rate of about 10 MHz and can be implemented with a single integrated circuit if 2-.mu.m CMOS technology is used. Aside from the fact that a CMOS process with 2-.mu.m geometry is currently available only in research and development laboratories and, thus, is not yet suited for volume production of semiconductor devices, the maximum possible clock rate of about 10 MHz is too low if such data reduction circuits are to be used in circuits for eliminating flicker in a television picture. This requires higher clock rates which range from about 17 MHz to 20 MHz.
In the prior arrangement, the time-critical loop, which limits that maximum clock rate, contains a subtracter, an adder, a limiter, and a quantizer. This loop must perform the necessary computations within one period of the clock signal, which is only about 100 ns in the prior art arrangement if correspondingly fast adder/subtracter stages are used.